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EL4543
Data Sheet September 13, 2007 FN7325.11
Triple Differential Twisted-Pair Driver with Common-Mode Sync Encoding
The EL4543 is a high bandwidth triple differential amplifier with integrated encoding of video sync signals. The inputs are suitable for handling high speed video or other communications signals in either single-ended or differential form, and the common-mode input range extends all the way to the negative rail enabling ground-referenced signalling in single supply applications. The high bandwidth enables differential signalling onto standard twisted-pair or coax with very low harmonic distortion, while internal feedback ensures balanced gain and phase at the outputs reducing radiated EMI and harmonics. Embedded logic encodes standard video horizontal and vertical sync signals onto the common mode of the twisted pair(s), transmitting this additional information without the requirement for additional buffers or transmission lines. The EL4543 enables significant system cost savings when compared with discrete line driver alternatives. The EL4543 is available in both a 24 Ld QSOP package and a 20 Ld QFN package and is specified for operation over the -40C to +85C temperature range.
TABLE 1. SYNC SIGNAL ENCODING COMMON MODE A (RED) 3.0 2.5 2.0 2.5 COMMON MODE B (GREEN) 2.0 3.0 3.0 2.0 COMMON MODE C (BLUE) 2.5 2.0 2.5 3.0
Features
* Fully differential inputs, outputs, and feedback * 350MHz -3dB bandwidth * 1200V/s slew rate * -75dB distortion at 5MHz * Single 5V to 12V operation * 50mA minimum output current * Low power - 36mA total typical supply current * Pb-free available (RoHS compliant)
Applications
* Twisted-pair drivers * Differential line drivers * VGA over twisted-pair * Transmission of analog signals in a noisy environment
Ordering Information
PART NUMBER EL4543IU EL4543IU-T7** EL4543IU-T13** EL4543IUZ (See Note) EL4543IUZ-T7** (See Note) EL4543IUZ-T13** (See Note) EL4543IL PART MARKING EL4543IU EL4543IU EL4543IU EL4543IUZ EL4543IUZ EL4543IUZ 4543IL 4543IL 4543IL 4543ILZ 4543ILZ 4543ILZ PACKAGE 24 Ld QSOP 24 Ld QSOP 24 Ld QSOP 24 Ld QSOP (Pb-free) 24 Ld QSOP (Pb-free) 24 Ld QSOP (Pb-free) 20 Ld 4x4 QFN* 20 Ld 4x4 QFN* 20 Ld 4x4 QFN* 20 Ld 4x4 QFN* (Pb-free) 20 Ld 4x4 QFN* (Pb-free) 20 Ld 4x4 QFN* (Pb-free) PKG. DWG. # MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 L20.4x4B L20.4x4B L20.4x4B L20.4x4B L20.4x4B L20.4x4B
H Low Low High High
V High Low Low High
TABLE 2. INPUT LOGIC THRESHOLD (+5V SUPPLY) VLO, max VHI, min 0.8V 2V
EL4543IL-T7** EL4543IL-T13** EL4543ILZ (See Note) EL4543ILZ-T7** (See Note) EL4543ILZ-T13** (See Note)
*20 Ld 4x4 QFN, exposed pad 2.7 x 2.7mm is connected to VS**Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004-2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL4543 Pinouts
EL4543 (24 LD QSOP) TOP VIEW
EN 1 VINA+ 2 VINA- 3 NC 4 VSYNC 5 HSYNC 6 NC 7 VINB+ 8 VINB- 9 NC 10 VINC+ 11 VINC- 12 + + + 24 VOUTA+ 23 VOUTA22 NC 21 VS+ 20 VS19 NC 18 VOUTB+ 17 VOUTB16 NC 15 VOUTC+ 14 VOUTC13 NC VSYNC 1 HSYNC 2 NC 3 VINB+ 4 VINB- 5 VOUTC+ 10 VINC+ 6 VINC- 7 NC 8 VOUTC- 9 THERMAL PAD
EL4543 (20 LD QFN) TOP VIEW
17 VOUTA+ 16 VOUTA15 VS+ 14 VS13 NC 12 VOUTB+ 11 VOUTB19 VINA+
20 VINA-
2
18 EN
FN7325.11 September 13, 2007
EL4543
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS+ & VS-). . . . . . . . . . . . . . . . . . . . . . . . . . . .+12V Maximum Output Continuous Current . . . . . . . . . . . . . . . . . . 70mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C VIN+, VINB . . . . . . . . . . . . . . . VS- + 0.8V (min) to VS+ - 0.8V (max) VIN- - VINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW (-3dB) SR TSTL GBW HD2 HD3 dP dG -3dB Bandwidth
VS+ = +5V, VS- = 0V, TA = +25C, VIN = 0V, RL = 150, unless otherwise specified. CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT
DESCRIPTION
VOUT = 2VP-P RL = 200 600
350 1000 13.6 700
MHz V/s ns MHz dBc dBc %
Differential Slew Rate Settling Time to 0.1% Gain Bandwidth Product 2nd Harmonic Distortion 3rd Harmonic Distortion Differential Phase @ 3.58MHz Differential Gain @ 3.58MHz
f = 20MHz, RL = 200 f = 20MHz, RL = 200
-70 -70 0.01 0.01
INPUT CHARACTERISTICS VOS IIN ZIN CIN VDIFF VCM VN CMRR EN Input Referred Offset Voltage Input Bias Current (VIN+, VIN+) Differential Input Impedance Input Capacitance Differential Input Range Input Common Mode Voltage Range Input Referred Voltage Noise Input Common Mode Rejection Ratio Threshold VCM = 0 to 2V 60 VS+ = +5V, VS- = 0V. See Figure 7 for higher supply voltages. 0 27 80 1.4 Capacitance between any single input pin and the power supplies -10 -30 2 -15 180 4 0.75 2.3 10 -10 mV A k pF V V nV/Hz dB V
OUTPUT CHARACTERISTICS IOUT COUT Output Peak Current Output Capacitance (Disabled) Capacitance between any single output pin and the power supplies when disabled 40 60 12 mA pF
DC PERFORMANCE AV Voltage Gain VIN = 0.8VP-P 1.82 1.96 2.05 V/V
SUPPLY CHARACTERISTICS VSUPPLY IS PSRR NOTE: 1. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. Supply Operating Range Power Supply Current (per Channel) Power Supply Rejection Ratio VS+ to VS5 12.3 70 14.5 80 12 16.2 V mA dB
3
FN7325.11 September 13, 2007
EL4543 Pin Descriptions
QFN QSOP PIN NUMBER PIN NUMBER 18 1 PIN NAME EN PIN DESCRIPTION Disables video inputs and outputs
EN
EQUIVALENT CIRCUIT
VSM CIRCUIT 1
19 20 3, 8, 13 1
2 3 4, 7, 10, 13, 16, 19, 22 5
VINA+ VINANC VSYNC
Non-inventing input Inverting input Not connected Vertical sync logic input
SYNC
VSM CIRCUIT 2
2 4 5 6 7 9 10 11 12 14, Thermal Pad 15 16 17
6 8 9 11 12 14 15 17 18 20 21 23 24
HSYNC VINB+ VINBVINC+ VINCVOUTCVOUTC+ VOUTBVOUTB+ VSVS+ VOUTAVOUTA+
Horizontal sync logic input Non-inverting input Inverting input Non-inverting input Inverting input Inverting output Non-inverting output Inverting output Non-inverting output Negative supply Positive supply Non-inverting output Inverting output
Reference Circuit 2
4
FN7325.11 September 13, 2007
EL4543 Typical Performance Curves
-42 BALANCE ERROR = 20 LOG(VO,CM/VO,DIFF) BALANCE ERROR (dB) VOLTAGE (0.5V/DIV) BLUE CM OUT (CH C) GREEN CM OUT (CH B) RED CM OUT (CH A) VSYNC HSYNC TIME (0.5ms/DIV) -46
-50
-54
VOLTAGE (2.5V/DIV)
-58
-62 100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 1. COMMON MODE OUTPUT
FIGURE 2. BALANCE ERROR
4 CL = 0pF NORMALIZED GAIN (dB) 2 RL = 500 NORMALIZED GAIN (dB) RL = 200
4 RL = 200 2 12pF 8.2pF 0 2.2pF -2 22pF
0 RL = 100 -2 RL = 50 -4
-4
-6 100k
1M
10M
100M
1G
-6 100k
1M
10M
100M
1G
FREQUENCY RESPONSE (Hz)
FREQUENCY RESPONSE (Hz)
FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS RL - DIFF
FIGURE 4. DIFFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS CL - DIFF
4 RL = 100 CL = 2.2pF NORMALIZED GAIN (dB) 2 12pF 8.2pF NORMALIZED GAIN (dB) 4.7pF
0 RL = 200 20
0 2.2pF -2
40
60
-4
80
-6 100k
1M
10M
100M
1G
100 100k
1M
10M
100M
1G
FREQUENCY RESPONSE (Hz)
FREQUENCY RESPONSE (Hz)
FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS CL - DIFF
FIGURE 6. CMRR
5
FN7325.11 September 13, 2007
EL4543 Typical Performance Curves
12 THRESHOLD (V) RELATIVE TO NEGATIVE SUPPLY 10 8 CMIR (V) 6 4 2 0 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V)
(Continued)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) VSWITCH
FIGURE 7. COMMON MODE INPUT RANGE vs SUPPLY VOLTAGE
FIGURE 8. HSYNC & VSYNC THRESHOLD vs SUPPLY VOLTAGE
0
45 40
-20 PSRR (dB)
SUPPLY CURRENT (mA)
35 30 25 20 15 10 5 RL = 200 0 1 2 3 4 5 6 7 8 9 10 11 12
-40
-60
-80
-100 0 10k 100k 1M 10M 100M FREQUENCY (Hz)
0
SUPPLY VOLTAGE (V)
FIGURE 9. PSRR vs FREQUENCY
FIGURE 10. ISUPPLY vs VSUPPLY
3.5 ENABLE DISABLE PIN (V) 3.0 VOLTAGE (2V/DIV) 2.5 2.0 1.5 1.0 0.5 0 5 6 7 8 9 10 11 12 TIME (200ns/DIV) SUPPLY VOLTAGE (V) 2.5V 212ns ENABLE OUTPUT SIGNAL
FIGURE 11. ENABLE DISABLE vs SUPPLY VOLTAGE
FIGURE 12. ENABLE RESPONSE
6
FN7325.11 September 13, 2007
EL4543 Typical Performance Curves
(Continued)
ENABLE VOLTAGE (2V/DIV) 2.5V 900ns VOLTAGE (120mV/DIV)
RL = 200 DIFF CL = 0pF
RISE t = 2.5ns
FALL t = 1.94ns
OUTPUT SIGNAL
TIME (200ns/DIV)
TIME (20ns/DIV)
FIGURE 13. DISABLE RESPONSE
FIGURE 14. DIFFERENTIAL SMALL SIGNAL TRANSIENT RESPONSE
9 COMMON MODE DC LEVEL (V) RL = 200 DIFF CL = 0pF VOLTAGE (235mV/DIV) LOGIC HSYNC = 0V 8 VSYNC = 0V 7 6 5 4 3 2 1 0 TIME (20ns/DIV) 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V)
N EE GR -B CM ED -A R CM UE C BL C M-
RISE t = 2.81ns
FALL t = 2.31ns
FIGURE 15. DIFFERENTIAL LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 16. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE
9 COMMON MODE DC LEVEL (V) COMMON MODE DC LEVEL (V) LOGIC HSYNC = 0V 8 VSYNC = 3V 7 6 5 4 3 2 1 0 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V)
D RE -A CM L UE -C B CM EEN B GR C M-
9 LOGIC HSYNC = 3V 8 VSYNC = 0V 7 6 5 4 3 2 1 0 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V)
N EE GR M- B C L UE -C B CM D A RE C M-
FIGURE 17. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE
FIGURE 18. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE
7
FN7325.11 September 13, 2007
EL4543 Typical Performance Curves
9 COMMON MODE DC LEVEL (V) LOGIC HSYNC = 3V 8 VSYNC = 3V OUTPUT IMPEDANCE () 7 6 5 4 3 2 1 0 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) 0 10k 100k 1M FREQUENCY (Hz) 10M 100M
C M- C UE BL
(Continued)
50 AV = +2 40
ED -A R CM N REE BG C M-
30
20
10
FIGURE 19. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE
FIGURE 20. OUTPUT IMPEDANCE
1M OUTPUT IMPEDANCE () 100k 10k 1k 100 10 1 10k CHAN A, B, C
0 RL = 200 DIFF -20 CROSSTALK (dB) 100k 1M FREQUENCY (Hz) 10M 100M
-40
-60
-80
-100 100k
1M
10M FREQUENCY (Hz)
100M
400M
FIGURE 21. OUTPUT IMPEDANCE [DISABLED]
FIGURE 22. CHANNEL ISOLATION vs FREQUENCY
10k VOLTAGE NOISE (nV/Hz), CURRENT NOISE (pA/Hz)
5
NORMALIZED GAIN (dB)
1k
3
1
VOP-P = 200mV
100
-1 VOP-P = 2V -3
10
1 5 6 7 8 9 10 12 FREQUENCY (Hz)
-5 100k
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 23. INPUT VOLTAGE AND CURRENT NOISE
FIGURE 24. FREQUENCY RESPONSE vs OUTPUT AMPLITUDE
8
FN7325.11 September 13, 2007
EL4543 Typical Performance Curves
(Continued)
FIGURE 25. GAIN vs FREQUENCY - 2 CHANNELS
FIGURE 26. GAIN vs FREQUENCY - 2 CHANNELS
FIGURE 27. GAIN vs FREQUENCY - 2 CHANNELS
FIGURE 28. PHASE vs FREQUENCY - 2 CHANNELS
FIGURE 29. PHASE vs FREQUENCY - 2 CHANNELS
FIGURE 30. PHASE vs FREQUENCY - 2 CHANNELS
9
FN7325.11 September 13, 2007
EL4543 Typical Performance Curves
(Continued)
FIGURE 31. HARMONIC DISTORTION
FIGURE 32. HARMONIC DISTORTION
1.4 POWER DISSIPATION (W) 1.2 1 0.8 0.6 0.4 0.2 0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.136W
JA =
Q SO P 88 24 C /W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 33. HARMONIC DISTORTION
FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 POWER DISSIPATION (W) 1 870mW 0.8
0.8 POWER DISSIPATION (W)
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD
0.7 667mW 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
(4 Q m
0.6 0.4 0.2
JA =
QS
11
OP C/
F JA m x N2 0 =
5
24
15 4m 0 C m) /W
W
FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 36. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
10
FN7325.11 September 13, 2007
EL4543 Typical Performance Curves
(Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3 2.500W POWER DISSIPATION (W) 2.5 2 1.5 1 0.5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
(4 Q mF mN 2 =4 x 4 0 0 mm C /W )
JA
FIGURE 37. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Operational Description and Application Information
Introduction
The EL4543 is designed to differentially drive composite RGB video signals onto twisted pair lines, while simultaneously encoding horizontal and vertical sync signals as common mode output. The entire video signal plus sync can therefore be transmitted on 3 twisted pairs of wire. When utilizing CAT5 cable, the 4th available twisted pair can be used for transmission of audio, data or control information. The distribution of composite video over standard CAT5 cable enables enormous cost and labor savings compared with traditional coaxial cable, when considering both the relative low price and ease of pulling CAT5 cable.
differential output signals, decoded and transmitted along with the RGB video signals to the video monitor.
ENABLE/DISABLE
+ INA -
EN + VREF
+ OUTA -
VSYNC HSYNC EN LOGIC DECODING
RCM GCM BCM
+ INB -
EN + VREF
+ OUTB -
Functional Description
The EL4543 provides three fully differential high-speed amplifiers, suitable for driving high-resolution composite video signals onto twisted pair or standard coaxial cable. The input common-mode range extends to the negative rail, allowing simple ground-referenced input termination to be used with a single supply. The amplifiers provide a fixed gain of +2 to compensate for standard video cable termination schemes. Horizontal and Vertical sync signals (HSYNC and VSYNC) are passed to an internal Logic Encoding Block to encode the sync information as three discrete signals of different voltage levels. Generally, in differential amplifiers an external VREF pin is used to control the common mode level of the differential output; in the case of the EL4543 the VREF of each of the three internal amplifier channels receives a signal from the Logic Encoding Block with encoded HSYNC and VSYNC information. The final output consists of three fully differential video signals, with sync encoded on the common mode of each of the three RGB differential signals. HSYNC and VSYNC can easily be separated from the 11
+ INC -
EN + VREF
+ OUTC -
FIGURE 38. BLOCK DIAGRAM EL4543
Sync Transmission
The EL4543 encodes HSYNC and VSYNC signals on the common mode output of the differential video signals; Red, Green and Blue respectively. Data Sheet Figures 16, 17 and 18 clearly illustrate that the sum of the common mode voltages results in a fixed average DC level with no AC content and illustrates the logic levels. This eliminates EMI radiation into any common mode signal along the twisted pairs of CAT5 cable.
FN7325.11 September 13, 2007
EL4543
Extract Common Mode Sync and Decode HSYNC and VSYNC
HSYNC and VSYNC can be regenerated from the Common Mode sync output voltages. The relationships between HSYNC, VSYNC and the 3 common mode levels are given by Table 1. The common mode levels are easily separated from the differential outputs of the EL4543 using this simple resistor network at the cable receiver input of each differential channel; see Figure 39. EL9110's common mode output pin, decodes and transmits HSYNC and VSYNC to the output device.
Sync Transmission
The EL4543 encodes HSYNC and VSYNC signals onto the common mode output of the differential video signals; Red, Green and Blue respectively. Data Sheet Figure 8 clearly illustrates that the sum of the common mode voltages results in a fixed DC level with no AC content; thus eliminating EMI interference.
Twisted Pair Termination
The schematic in Figure 39 illustrates a termination scheme for 50 series termination and a 100 twisted pair cable. Note RCM is the common mode termination to allow measurement of VCM and should not be too small since it loads the EL4543; a little over a 100 is recommended for RCM.
TYPICAL EL4543 TERMINATION DRIVER 50 + 50 VREF TWISTED PAIR ZO =100 + 50 VCM 50 120 (RCM: SHOULD BE >100) (FOR LOADING CONSIDERATIONS)
Output Drive Protection
The EL4543 has internal short circuit protection set typically at 60mA. if the output is shorted for extended periods of time the increased power dissipation will eventually destroy the part. To realize maximum reliability the output current should never exceed 60mA. The 50 series back load matching resistor provides additional protection.
Supply Voltage
While the EL4543 can be operated on 5V split rails, single supply 0V to 5V is the most common usage. It is very important to note that the input logic thresholds are relative to the negative supply pin, and therefore single supply, ground referenced logic will not work when driving the EL4543 on split rails. The amplifiers have an input common mode range from 0V to 2.3V with a 0V to 5V supply, increasing with supply voltage (see Figure 7). The common mode output DC level range is a linear function of the power supply (see Figures 16, 17, 18, and 19). The common mode input switching threshold as well as the Enable/Disable input is a linear function of the supply voltage (see Figures 8 and 11). In the event that the EL4543 is to be used with 5V split rails then the input sync signals need to be voltage offset before they are input to the EL4543. The circuit configuration depicted in Figure 40 provides for the proper level shift.
FIGURE 39. TWISTED PAIR TERMINATION EL4543
Video Transmission
The EL4543 is a twisted pair differential line driver directed at the transmission of Video Signals through cables up to 100 feet; however, as signal losses increase with transmission line length the EL4543 will need additional support to equalize video signals along longer twisted pair transmission lines. A full solution to accomplish this is the SXGA Video Transmission System presented in the EL4543 Data Sheet. Note the inclusion of the EL9110 for signal equalization of up to 1000ft of CAT5 cable and common mode extraction; see Data Sheet for additional information on the EL9110.
Long Distance Video Transmission
The SXGA Video Transmission System makes it possible to transmit Red, Green and Blue (RGB) video plus sync up to 1000 feet through CAT5 cable. The input to the SXGA Video Transmission System is the output of a video source transmitting RGB video signals plus sync. The signals are received initially by the EL4543; which converts the single ended input RGB signals to three fully differential waveforms with sync encoded on the discrete common modes of each color channel and then drives the signals through a length of CAT5 cable. The signal is received by the EL9110, which can provide 6-pole equalization for both high and low frequency signal transmission line losses. Then the EL9110 converts the differential RGB video signals back into single ended format while extracting the common mode component for decoding. The single ended RGB signal is taken directly from the output of the El9110 and is ready for the output device. The Common Mode Decoder Circuit receives the common mode signals directly from each of the three 12
Horizontal Sync in 4.30k
KST2907A 2.70k
EL4543 HSYN Pin
-5V
Vertical Sync in 4.30k
KST2907A 2.70k
EL4543 VSYN Pin
-5V
FIGURE 40. LEVEL SHIFTING SYNC SIGNALS FOR USE WITH 5V SPLIT RAILS
FN7325.11 September 13, 2007
EL4543
Disable and Power Down
The EL4543 provides an enable disable function which powers down, logic input high, in 900ns and powers up, logic input low, in 212ns. Disabled the amplifiers supply current is reduced to 1.8mA (Positive Supply) and 0mA (Negative Supply). Note that Enable/Disable threshold is a linear function of the supply voltage levels. The Enable/Disable threshold voltage level is compatible with standard TTL/CMOS and referenced to the lowest supply potential. Having obtained the application's power dissipation, the maximum junction temperature can be calculated:
T JMAX = T MAX + JA x PD (EQ. 2)
where: * TJMAX is the maximum junction temperature (125C) * TMAX is the maximum ambient operating temperature * PD is the power dissipation calculated above * JA is the thermal resistance, junction to ambient, of the application (package + PCB combination). Refer to the Package Power Dissipation curves. * Note: For the QFN package, the thermal pad is internally connected to VS- and may only be grounded in applications where a single supply is used and VS- is returned to ground. In applications where VS- is tied to a negative voltage the thermal pad must also be connected to the same negative voltage. See Technical Bulletin 389 (http://www.intersil.com/data/tb/TB389.pdf) for additional QFN PCB layout information.
Proper Layout Technique
A critical concern with any PCB layout is the establishment of a "healthy" ground plane. It is imperative to provide ground planes terminated close to inputs to minimize input capacitance. Additionally, the ground plane can be selectively removed from inputs to prevent load and supply currents from flowing near the input nodes. In general the following guidelines apply to all PCB layout: * Keep all traces as short as possible. * Keep power supply bypass components as close to the chip as possible - extremely close. * Create a healthy ground with low impedance and continuous ground pathways available to all grounded components board-wide. * In high frequency applications on multi-level boards try to keep one level of board with continuous ground plane and minimum via cutouts - providing it is affordable. * Provide extremely short loops from power pin to ground. * If it is affordable, a ferrite bead is always of benefit to isolate device from Power Supply noise and the rest of the circuit from the noise of the device.
Application Circuit
Video Transmission Along CAT5 Cable
VGA input RGB plus sync is connected with 75 termination to the inputs of the EL4543. Single-ended RGB video is converted to differential mode signals with HSYNC and VSYNC encoded on the common-mode of the three differential signals, respectively. The 50 output-terminated EL4543 drives the differential RGB with sync encoded common-mode to CAT5 twisted pair cables. Note this system, without signal frequency equalization, will satisfactorily transmit along up to 200ft of CAT5 twisted-pair. For longer cable lengths, frequency and gain equalization to compensate for signal degradation is recommended (EL9110) and a delay line technology (EL9115) to adjust for phase mismatch between signals at the receiving end.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the EL4543 drive capability is ultimately limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (125C). It is necessary to calculate the power dissipation for a given application prior to selecting package type. Power dissipation may be calculated:
V O PD = 3 x V S x I SMAX + V S x ----------- R LD (EQ. 1)
where: * VS is the total power supply to the EL4543 (from VS+ to VS-) * ISMAX = Maximum quiescent supply current per channel * VO = Maximum differential output voltage of the application * RLD = Differential load resistance * ILOAD = Load current
13
FN7325.11 September 13, 2007
EL4543 and EL9110 Sync Extraction
CAT1
RJOUTA+ 49.9
CAT2
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
1
EN INA+ INAN.C.
EL4543 QSOP
OUTA+ OUTAN.C. VS+ VS-
24 23 22 21 20 19 18 17 16 15 14 13
R32
75
RED
RJA+ 75
2 3
Red Out Differential
RJOUTA49.9
1
VS+
8
C34 0.1uf
+VS R31 75
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GREEN
4 5
RVSYNC 1K
2 +VS 0.1uf C35 3
_
7
VSYNC HSYNC N.C. INB+ INBN.C. INC+ INC-
_
6
EL4543IU
6
RHSYNC 1K
N.C. OUTB+ OUTBN.C. OUTC+ OUTCN.C.
7 8
RJB+ 75
RJOUTB+ 49.9
4
VS-
5 C35a 200pF
RED GREEN BLUE R29 2K R30 2K
Green Out Differential
RJOUTB49.9 RJOUTC+ 49.9
EL8201IS
U3
INPUT
9 10 11
Blue Out Differential
RJOUTC49.9
HSYNC VSYNC
BLUE
RJC+ 75
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
3000
330
R7
R8
75 R24
INDUCTOR 4
C30
Blue In Differential
Green InDifferential
Red In Differential
R13
INDUCTOR 2
EL9110
EL9110
R6 1K R5 1uf C4 49.9 R3 49.9 NL C3 C2 0.1uf NL R4 R9 330 C5 1uf
C15
+VS
R17 49.9 NL C14
1uf
51 R11
Ctrl-ref Vctrl Vinp Vinm Vsm Cmout Vgain Logic-ref
Cmext Vsp Enbl Vspo Vout Vsmo 0V X2
R30 1K R29
C10
C13
0.1uf
51 R22
C22
49.9
EL9110 BLUE C
C6 0.1uf -VS INDUCTOR 1
NL R18 R20 330 C16 1uf
Ctrl-ref Vctrl Vinp Vinm Vsm Cmout Vgain Logic-ref
Cmext Vsp Enbl Vspo Vout Vsmo 0V X2
R32 +VS C21 0.1uf 0.1uf R31 49.9 R28 49.9 NL C25 C24
1K
0.1uf NL R29 R27 330
51 C33 1uf R33
Ctrl-ref Vctrl Vinp Vinm Vsm Cmout Vgain Logic-ref
Cmext Vsp Enbl Vspo Vout Vsmo 0V X2
EL9110
R26
R1 49.9
NL R2
BLUE
51 R10 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
5 R14
R15 49.9
NL R16
51 R21
GREEN
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
R25
NL C1
5
NL C12
R19
330
75
1uf
R26 49.9
NL C23
NL R27
RED
51 R32 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
5
INDUCTOR 6
R31 330
Rred4 3000
1uf
C9
75 R25
0.1uf
C11
0.1uf
14
-VS DIODE D1 +VS DIODE D3
12
OUTPUT
-VS DIODE D9 +VS DIODE D10 -VS DIODE D11 DIODE D12 +VS
UJ1
+VS DIODE D2 -VS DIODE D4 VCRTL VadjBlu +VS DIODE D7 DIODE D8 -VS DIODE D5 DIODE D6 -VS VCRTL C20 1uf +VS
EL4543
VCRTL
VadjRed
0.1uf C31
0.1uf C32
+VS
EL9110 GREEN B
C17 0.1uf -VS INDUCTOR3
EL9110 RED A
C27 0.1uf -VS INDUCTOR 5
VGAN
VGAN
VGAN
C26 1uf C19 0.1uf
C7 1uf
5 R12 C8 0.1uf
C18 1uf
5 R23
C28 1uf
5 R28
C29 0.1uf
+VS NL = Not Loaded Inductor =Ferrite 68 Ohms R33 3.6K
+VS +VS R34 3.6K +VS R35 3.6K BANANA JACK GND BANANA JACK R37 VadjBlue 1K Pot VGAN R38 1K Pot VCRTL -VS BANANA JACK + C36
4.7uf
+VS
C37
0.1uF
+VS R39 3.6K
R36 1K Pot
+ C38
4.7uf
C39
0.1uF
R40 1K Pot -VS
VadjRed
FN7325.11 September 13, 2007
EL4543 EL4543/EL5375/EL8201 CAT5 RGB + Sync Video Transmission System
Introducing a low cost turn-key system for transmitting component video over short to moderate CAT5 cable lengths (1 to 500 feet) with selectable cable loss and skew compensation. Using only 3 of the 4 pairs in standard CAT5 the 4th pair is available for audio, function control or data transmission; an additional benefit. RGB video plus sync (5 channels) is received at the VGA terminal and presented single ended to the EL4543. The EL4543 converts single ended RGB into fully differential signals on three twisted pairs. Sync is encoded on the three RGB differential signals as differential common mode and then drives the differential signals with encoded sync through CAT5 cable. The common mode of the signals is extracted from the differential signals with a passive network of resistors and passed to the EL8201 for sync decoding. The differential signal is passed directly to the EL5375 where it is amplified, converted back into single ended format. Signal attenuation occurs in all transmission lines as a function of increasing cable length; this application system utilizes individual channel 2-pole compensation for cable lengths of 150, 300 and 500 feet. Additionally, the compensation network can be manipulated to provide some measure of cable prop delay skew compensation for slight differences in cable lengths between CAT5 pairs. Cable skew can best be done around the 300ft range by under compensating the shortest color pair (color on the left side of a vertical line) and over compensate the longest color pair (color on the right side of a vertical line). Around 450ft only the shortest color pair can be under compensated. The board for the driver and receiver should use strip lines or strip line waveguides for the inputs and outputs of the drivers and receivers. The 75 input and output strip lines waveguide on 0.06 inch epoxy board with ground back plain should be 0.016 inch wide with 0.01 inch space to ground area around them. The differential pair strip line waveguides should be two 0.045 inch 50 lines spaced 0.01 inch apart and spaced 0.01 inch to ground area around them. This is a general guide and size values may very for many reasons. The receiver feedback and gain resistor network which goes directly to the minus input should be connected very close with minimal trace length and minimal capacitance to ground. The ground plane on the backside of the board, in back of these resistors and the minus input pin should be removed as well.
15
FN7325.11 September 13, 2007
EL4543/EL5375/EL8201 CAT5 RGB + Sync Video Transmission System
Output +5V R34 Open R35 0 2 3 Output +5V 499 R28 2K R25 R28 2K R12 57 R13 57 R24 R36 Open R37 0 6 R14 49.9 7 R21 1K R30 2K R26 2K R27 Output +5V R38 Open R39 0 10 11 R15 57 R16 57 12 INP3 INN3 NC EN FB3 OUT3 15 14 13 R45 2K R51 1K R52 500 8 9 INP2 INN2 NC REF3 VSN NC FB2 OUT2 19 499 4 5 INP1 INN1 NC REF2 FB1 OUT1 NC VSP 23 22 21 Output +5V 20 C6 0.1uF R43 2K C5 0.1uF R41 2K C20 ~4pF 1 U2 REF1 NC 24 R40 2K
R47 500
R48 1K R53
150 Feet Comp 10K
300 Feet Comp R55 C9 68p 3.9K C10 22p R56 33K
C7 C8 36p 10p
R54 68K
Output -5V 18 17 16
499 R31
499
C2 0.1uF
C21 ~4pF
R44 2K
R49 500
R50 1K
Compensation Control Switch On Off 1 12 2 11 3 10 4 9 5 8 6 7 SW DIP-6
150 Feet Comp R57 C11 36p 10K C12 10p R58 68K
300 Feet Comp R59 C13 68p 3.9K C14 22p R60 33K
INPUT
R4 75
9 10
INBN.C. INC+ INC-
N.C. OUTC+ OUTCN.C.
16 15 14
R9 49.9 R10 49.9
R32
499 R33
INB+
OUTB-
499
JB3 GND
Csup1 4.7uF
1
2
1
1
Output +5V JB4 +VS Out + Csup3 4.7uF JB6 GND JB5 -VS Out
Output -5V
Csup4 4.7uF
2
8 7 6 5 4 3 2 1
OUTPUT
1 2 3 4 5 6 7 8
INPUT
2
+
+
16
Red In
1
R1 75
EN INA+ INAN.C.
EL4543 QSOP
OUTA+ OUTAN.C. VS+ VSN.C. OUTB+
24 23
R6 49.9
2 3 4 5
Red Out Differential
R7 49.9
EL5375
R17 49.9 C22 ~4pF R46 2K
300 Feet Comp R61 3.9K C15 C16 68p 22p
150 Feet Comp R63 R62 33K C17 36p 10K C18 10p R64 68K R63 R64 75 R65 75 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
22 21 20 19 18 17
Input +5V C1 0.1uf C3 0.1uF
R22 1K
R2 1K
VSYNC HSYNC N.C.
6
R3 1K
7
R8 49.9
R66 75 R18 55 R19 55
Green In
Green Out Differential
8
R67 75 C19 0.1uF 1 VS+ 8
OUTPUT
R20 49.9
Blue In
R5 75
11 12
Blue Out Differential
R11 49.9
2 C4 0.1uF R23 1K C4a 220pF
_
7
Output +5V
13
EL4543
3
_
6
EL4543IU
4
VS-
5
EL8201IS
U3
Input +5V JB1 +VS In + JP+ JUMPER JB2 -VS In
Input -5V
Csup2 4.7uF
JPJUMPER
Ground JUMPER
FN7325.11 September 13, 2007
EL4543
Package Outline Drawing
L20.4x4B
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/06
4X 4.00 A B 6 PIN 1 INDEX AREA 15 1 16 2.0 6 PIN #1 INDEX AREA
16X 0.50 20
4.00
2 .70 REF
11
5
(4X)
0.15 10 6 0.10 M C A B 4 20X 0.25 0.02
TOP VIEW
20X 0.4 0.05
BOTTOM VIEW
SEE DETAIL "X" 0.10 C C BASE PLANE SEATING PLANE 0.08 C ( 20X 0 . 5 )
0 . 90 0 . 1 ( 3. 8 TYP ) ( 2. 70 )
SIDE VIEW
( 20X 0 . 25 )
C
0 . 2 REF
5
( 20X 0 . 6)
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
17
FN7325.11 September 13, 2007
EL4543 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 44 DETAIL X
A1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN7325.11 September 13, 2007

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